Ahead V5000 version A & B.
Allows up to four boards in one system.
103h (R/W): Multiple Chip ID Register
bit 0-3 Must match PowerUp register (3CEh index 1Fh bits 4-7).
3C2h (W): Misc Output Register
bit 5 Bit 0 of bank register. (Ahead A)
Note: This register can be read at 3CCh.
3CEh index Ch (R/W): mode
bit 0-1 Misc control. 0=standard text mode, 1=enable
8 simultaneous fonts 2&3 reserved.
2 Reserved
3 High speed sequencer enable
4 16 bit memory access enable
5 Enhanced mode enable
6-7 Emulation mode. 0=VGA, 1=EGA, 2=Hercules and 3=CGA
3CEh index Dh (R/W): Segment (Different for Ahead A and B)
bit 0-2 (Ahead A) Bank No. bit 1-3
Bit 0 is in 3C2h bit 5.
0-3 (Ahead B) Read Bank No.
4-7 (Ahead B) Write Bank No.
3CEh index Eh (R/W): Clock
bit 1-3 Reserved
4-7 Divide input clock 0-3 by 2.
3CEh index Fh (R/W): Master Enable Register
bit 0-3 Chip version number (Read Only)
0=Ahead A, 1=Ahead B
5 Enable extended registers if set
3CEh index 10h (R/W): Trap
bit 0 Enable CRTC access
1 Enable 6845 access
2 Enable CRTC access to cause trap
3 Enable 3B8h, 3BFh to cause trap
4 Enable 3D8h, 3D9h to cause trap
5 Enable 3Cxh to cause traps
7 Select 6845 as CRT controller
3CEh index 11h (R/W): Trap source
bit 0 3Dxh
1 3B5h, 3D5h
2 3B8h, 3D8h
3 3D9h
4 3BFh
5 3Cxh
6-7 Reserved
3CEh index 12h (R/W): Attribute
bit 0-5 Reserved
6 Lock VGA internal palette
7 Enable CGA palette when in CGA mode
3CEh index 13h (R/W): Diagnostics
bit 0-7 Reserved
3CEh index 14h (R/W): Lock
bit 0 Lock Sync polarity in 3C2h bit 6,7.
1 Lock CRTC horizontal timing
2 Lock CRTC vertical timing
3 Lock CRTC index 9 !Hmm.
4 Lock CRTC index 9
5 Lock CRTC index 0Ah, 0Bh
6 Lock CRTC index 13h
7 Lock Clock select in 3C2h bit 2,3.
3CEh index 15h (R): 3B8/3D8 Readback
bit 0-7 Mono/CGA register 3B8h/3D8h readback value
3CEh index 16h (R): 3BF/3D9 Readback
bit 0-5 CGA Register 3D9h readback
6-7 Mono register 3BFh bit 0-1 Readback.
3CEh index 17h (R/W): Miscellaneous
bit 0 Must be 1
1 Must be 0
2-7 Reserved
3CEh index 1Ch (R/W): CRTC Control
bit 0-1 Bit 16-17 of CRTC start address
2-3 0=normal, 3=Interlaced, 1&2 reserved.
3CEh index 1Dh (R/W): Control
bit 0-7 Reserved
3CEh index 1Eh (R/W): Scratch
bit 0-7 Used by BIOS for flags
3CEh index 1Fh (R): PowerUp
bit 0-1 Memory type. 0=2x44256 (256k), 1=4 or 16 x44256 (512K/2M),
2=8 or 16 x4464 (256K or 512K), 3=8x44256 (1M)
2 0 for 24k BIOS, 1 for 32k BIOS.
3 16 bit BIOS
4-7 Multiple Chip ID
0= ID 0 BIOS Enabled, 1=ID 1 BIOS Enabled
2..15 ID 2..15 Bios Disabled.
46E8h (R/W): Setup Control Register
bit 3 0 for VGA disabled, 1 for enabled
4 0 for Setup mode, 1 for normal mode.
5-7 Reserved
Bank switching:
The Ahead A has one bank register with bit 0 in 3C2h bit 5 and
bits 1-3 in 3CEh index 0Dh.
The Ahead B has separate read and write banks in register 3CEh index Dh.
Memory locations:
$C000:$25 5 bytes 'AHEAD'
ID Ahead chipset:
old:=rdinx($3CE,$F);
wrinx($3CE,$F,0);
if not testinx2($3CE,$C,$FB) then
begin
wrinx($3CE,$F,$20);
if testinx2($3CE,$C,$FB) then
begin
case inp($3CF) and $F of
0:Ahead A;
1:Ahead B;
end;
end;
wrinx($3CE,$F,old);
Modes:
22h T 132 44 16 (8x8)
23h T 132 25 16 (8x14)
24h T 132 28 16 (8x)
25h G 640 480 16 planar
26h G 640 480 16 planar
2Fh T 160 50 16
32h T 80 34 16
33h T 80 34 16
34h T 80 66 16
42h T 80 34 4
43h T 80 45 4
50h T 132 25 2
51h T 132 28 4
52h T 132 44 2
60h G 640 400 256 P8
61h G 640 480 256 P8
62h G 800 600 256 P8
63h G 1024 768 256 P8 (Ahead B only)
6Ah G 800 600 16 PL4
70h G 720 396 16 PL4
71h G 800 600 16 PL4
74h G 1024 768 16 PL4
75h G 1024 768 4 PL2E
76h G 1024 768 2 PL1
Note: Mode 75h has even bytes in planes 0&2, and odd bytes in planes 1&3.